This invention relates generally to semiconductor devices and more particularly to a system and method for handling a power supply interruption in a non-volatile memory.
Non-volatile memories retain information in the absence of power. Examples of non-volatile memories include flash memory, erasable programmable read-only memory (EPROM), and electrically-erasable programmable read-only memory (EEPROM). Non-volatile memories may be used in a variety of electronic devices, such as microcontrollers, to provide storage capability.
A typical non-volatile memory requires a relatively long period of time for an erase operation, as compared with the amount of time for a read or a write operation. Because of this, anon-recoverable malfunction can occur when power to the non-volatile memory is interrupted during an erase operation. This power interruption can occur for a variety of reasons. For example, with cellular telephones and other battery-operated devices, a user may inadvertently remove the battery while an erase operation is being performed.
Typical non-volatile memories may include certain types of NOR flash cells that can go into depletion after being erased. If just one NOR flash cell goes into depletion, the entire sector of cells, as well as any other cells sharing the same bit line, may be corrupted. This problem is generally overcome by a process known as compaction that is performed after the erase operation. However, if a power supply interruption occurs before the compaction is completed, non-recoverable malfunction may result.
Previous attempts to solve this problem have included the introduction of split-gate cells as replacements for the NOR flash cells. The split-gate cells do not go into depletion upon erasure. However, the use of split-gate cells has the disadvantages of increased area requirements and reduced performance in terms of speed as compared to the NOR flash cells.
Previous attempts to solve this problem have also included the use of software solutions that require either two arrays of flash or the placement of tracking bits in sectors other than those being erased. However, disadvantages associated with software solutions such as these include the consumption of flash memory for data and for programming, as well as increased time and power requirements. Additionally, these solutions increase the complexity of the associated hardware. All of these disadvantages result in an increased cost for the non-volatile memory.
In accordance with the present invention, a system and method for handling a power supply interruption in a non-volatile memory are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods. In particular, the power supply interruption problems associated with NOR flash cells are solved without increasing area requirements or lowering performance.
In one embodiment of the present invention, a system for handling a power supply interruption in a non-volatile memory is provided that includes a status indicator set for each sector of a non-volatile memory array. The status indicator set is operable to indicate a status for the sector and is independently erasable from the sector. A state machine is operable to perform operations on the sectors. The state machine is also operable to adjust the status indicator set for a sector prior to performing an operation on the sector to indicate an interruption status and to adjust the status indicator set for the sector after completing the operation to indicate a completed status.
Technical advantages of the present invention include providing an improved system for handling a power supply interruption in a non-volatile memory. In particular, a status indicator for a sector is marked prior to the performance of an operation and erased after successful completion of the operation. As a result, interrupted operations are detected at power up based on a marked status indicator. Thus, the power supply interruption problems associated with NOR flash cells are solved without increasing area requirements or lowering performance. In addition, the cost of the memory is reduced, as well as time and power requirements.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.